SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

DSP ASIC/FPGA DESIGN ENGINEER (SILICON ENGINEERING)

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 

The Starlink modem team is seeking motivated, proactive, and intellectually curious engineers who can work with world-class cross-disciplinary teams (firmware, architecture, design, validation, product engineering). In this role, you will implement system algorithms and silicon solutions for cutting-edge communication systems for deployment in space and ground infrastructures. These systems are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

• Participate in all phases of ASIC/FPGA design flow - from concept to mass production
• Develop high-level design requirements and block-level micro-architectures, partition design within ASIC/FPGA, and create specification documents
• Develop RTL designs using SystemVerilog, with emphasis on DSP and digital communication system blocks (frontend, physical layer, link layer, error correction, etc.)
• Optimize your designs for area, speed, and power to meet system requirements; analyze architectural trade-offs
• Develop test benches and test cases for block-level functional verification, emphasizing bit-matching and self-checking
• Verify DSP blocks against fixed-point MATLAB model, work in collaboration with systems engineers
• Collaborate with verification engineers to develop UVM-based top-level tests for your blocks
• Participate in SoC-level and FPGA top-level integration activities
• Prototype designs on FPGA, focusing on closely emulating the final product functionality
• Use scripting languages to achieve higher performance and improve productivity through automation
• Perform lint checking, CDC checking, logic equivalence checking, and other EDA tool-based checks
• Run implementation tools, such as Synopsys Design Compiler, Xilinx Vivado, and others; perform timing closure for your designs
• Work with backend/implementation teams to address synthesis, timing, layout, and DFT issues for ASICs
• Bring-up and validate ASICs and FPGAs in the lab, utilize various lab equipment
• Collaborate with software engineers in developing production software for your designs

BASIC QUALIFICATIONS:

• Bachelor's degree in an engineering discipline
• 1+ years of professional experience in SystemVerilog, Verilog or VHDL RTL design
• Experience designing DSP and/or digital communication system datapath blocks

PREFERRED SKILLS AND EXPERIENCE:

• Experience in working with ASICs and/or FPGAs
• Experience in designing DSP, digital communication system datapath blocks, and/or modem design
• Strong programming and scripting skills in most of these languages: MATLAB, Python, C/C++, Perl, Tcl, Make, Bash
• Understanding of clock domain crossing (CDC) techniques
• Experience in FPGAs, evaluation boards, and knowledge of FPGA design flow
• Understanding of different DSP architectures and tradeoffs (including transforms, filtering, sample rate conversion, etc.)
• Knowledge of different digital modulation techniques (e.g. PSK, QAM, OFDMA, etc.)
• Knowledge of wireless communications systems and standards (e.g. LTE, Wi-Fi, Bluetooth, etc.)
• Knowledge of forward error correction (FEC) blocks, such as LDPC, Turbo Codes, convolutional/Viterbi, and Reed-Solomon codecs
• Knowledge of industry standard interfaces, protocols, and architectures: PCIe, Ethernet, AMBA, DDR, etc.
• Experience in developing automated, self-checking test benches and/or UVM
• Experience in EDA tools such as simulators (e.g. Questa), lint checkers (e.g. Spyglass), synthesis (e.g. Design Compiler), FPGA tools (e.g. Vivado)
• Experience in formal verification and logic equivalence checking, knowledge of LEC tools (e.g. Formality)
• Knowledge of power optimization, power estimation, UPF-based power verification
• Experience in Git version control system
• Knowledge of synthesis and static timing analysis, knowledge of timing closure techniques for high-speed designs, knowledge of STA tools (e.g. PrimeTime)
• Experience in Atlassian collaboration and automation tools: JIRA, Confluence, Bitbucket, Bamboo, etc.
• Strong interpersonal/written/verbal communication skills and experience with cross-functional collaboration
• Strong teamwork skills combined with ability to work autonomously as an individual contributor
• High level of self-motivation and desire to be challenged and learn new skills
• Strong problem solving skills with high attention to detail
• Ability to work in a dynamic, fast-paced environment with changing needs and requirements
• Ability to meet tough goals under high pressure and manage time effectively

ADDITIONAL REQUIREMENTS:

• Must be willing to work extended hours and weekends as needed

COMPENSATION & BENEFITS:    Pay range:    DSP ASIC/FPGA Design Engineer/Level I: $130,000.00 - $155,000.00/per year  DSP ASIC/FPGA Design Engineer/Level II: $150,000.00 - $180,000.00/per year    

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

ITAR REQUIREMENTS:

• To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.  

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify the Human Resources Department at (310) 363-6000.