SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. 

SR. FPGA/ASIC VALIDATION ENGINEER (SILICON ENGINEERING) 

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to 2M+ users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious Validation engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering). In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.    

RESPONSIBILITIES:

• Design and build unique and technically challenging automated measurement systems, including both hardware and software design
• Propose and develop a longer-term software architecture for automated test infrastructure, encompassing instrument control, data capture, data analysis and data organization
• Develop hardware systems, PCBs and digital FPGA or microcontroller control solutions for the test systems
• Work closely with the FPGA/ASIC design team and flight software team to add/improve testability and define various test infrastructure logic to ensure adequate silicon test coverage
• Work closely with electrical design team to review signal integrity, power integrity and radiated/conducted emissions concerns as well as propose design changes or operational workarounds
• Evaluate new IP from internal and external IP providers and test for logical and electrical compatibility with existing chips and FPGAs
• Write software routines (Python, C/C++) to bring up and validate the SerDes while working with the software cross functional team members to help integrate SerDes drivers in the software track

BASIC QUALIFICATIONS:

• Bachelor’s degree in electrical engineering, computer engineering or computer science
• 5+ years of experience validating ASICs and/or FPGAs

PREFERRED SKILLS AND EXPERIENCE:

• Experience working with various high-speed SerDes architectures (NRZ, PAM4) and various clocking modes
• Working experience with Ethernet, PCIe and other high-speed protocol layers
• Ability to study and analyze internal and external team’s test results and provide interpretations to help drive IP selections and discussions
• Experience writing comprehensive test reports covering test boundary conditions and test results
• Strong debugging and problem-solving skills
• Strong object-oriented programming skills
• Strong communication skills and ability to work well within a fast-paced team
• Experience with serial digital communication protocols such as SPI, I2C, JTAG and/or the software/hardware solutions to exercise these
• Experience with microcontrollers, FPGAs, and/or basic digital signal processing concepts
• Experience developing multi-threaded applications and systems
• Experience with both Windows and Linux system usage/administration

ADDITIONAL REQUIREMENTS:

• Ability to work long hours and weekends as necessary to support critical milestones 

COMPENSATION AND BENEFITS:

Pay range:    ASIC/FPGA Validation Engineer/Senior: $160,000.00 - $220,000.00/per year    Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

ITAR REQUIREMENTS:

• To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.  

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status. 

Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should notify the Human Resources Department at (310) 363-6000.